Institute of Robust Power Semiconductor Systems

Real100G.COM is a DFG funded project aiming at reaching the data transmission speeds upto 100 Gbps at carrier frequencies of as high as 240 GHz. As a project partner, ILH is working on Synchronization of receiver by implementing Costas loops for BPSK and QPSK modulation types.

The project stands for realization of 100 Gbps wireless communications, funded in the context of the DFG priority program program.

Research Motivation

The need for true and reliable wireless receivers at ultra-high data rates upto 100 Gbps is an ambitious project for future scope. The channel between Transmitter and receiver introduces distortions to the signal being transmitted. These distortions include additive white noise, phase shift and frequency shift. Thus the received signal suffers from ISI and in worst cases the data is hard to recover or totally lost. This rises the need for synchronization between transmitter and receiver. 

Synchronization can be done very easily in digital domain where equilization techniques are used in order to estimate the constants and recover the data digitally. But this results in a complex and power hungry receiver system, which is also not a true wireless system. On the other hand, analog synchronizing scheme consume less power, compact in size and allows to integrate on chip along with receiver front end.


We at ILH, propose to apply the Costas loop and feedforward carrier recovery concepts in order to recover the phase and frequency information of the carrier signal in order to generate LO at the receiver end for synchronous reception.


The main goals of this project work are

  • Research on new data modulation scheme called PSSS with high spectral efficiencies in order to use the limited bandwidth.
  • Analog synchronizing scheme to synchronize LO signal between transmitter and receiver.
  • The baseband system to decode the received data

All the above goals are intended to design a complete receiver system which can able to reach data rates as high as 100 Gbps.

Used Methods

The synchronizing system design is done after rigorous analysis of different synchronizing schemes and adapting those schemes to our high data rate wireless transmission links. The synchronizing scheme is also compatible with the PSSS type modulation and baseband system for post processing of received data. The integrated circuit components required for the system are designed using our in house circuit design expertise in IHP SiGe 130 nm BiCMOS technology.

Further the project partners involve in the design of the base band system for symbol synchronization and post processing of the received data signals. The other project partner from IHP in Frankfurt (Oder) perform research on the PSSS data modulation scheme.

Project Members

This is a joint project of the groups of Prof. Kraemer at TU Cottbus and IHP, Prof. Kallfass at ILH, University of Stuttgart and Prof. Scheyyet at University of Paderborn.

This image shows Eswara Rao Bammidi

Eswara Rao Bammidi


Research Assistant

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