Dominik Koch

Abstract

In this work an easy to integrate and low-cost solution for an overcurrent detection in a high-current half-bridge module based on paralleled 100V, 7mΩ GaN HEMTs is presented. The overcurrent detection is realized with a simple pickup-coil which is integrated into the carrier PCB adjacent to the GaN transistors. The pickup-coils have a sensitivity of around 12mV/A, which results in a peak voltage of above 1.5V at 111A switched current and is twice as high as the peak voltage at the rated current of 50A per HEMT. By a comprehensive finite element s-parameter simulation up to 3GHz, the main coupling parameters between the pickup-coils and the surrounding structures are identified. For lower frequencies below 100MHz an inductive coupling between transistor and pickup-coil is higher, while for higher frequencies the capacitive coupling between inlay and pickup-coil is dominanting. A simple signal evaluation circuit based on an integration amplifier and a fast comparator is presented, which allows a very fast and reliable detection of overcurrent events in 24ns. The presented pickup coil has a significantly increased sensitivity to parasitic effects and coupling due to the high bandwidth of above 400MHz, but demonstrates a very simple implementation and shows the advantages of a non-invasive measurement and scalability for higher voltage classes.

Abstract

Design automation is becoming increasingly prevalent in addressing the ever-increasing requirements for efficiency and power density in modern power electronics. To achieve this, accurate loss models of the used power semiconductors are essential for soft- and hard-switching applications. While the double pulse test is a well-established fast electrical characterization method for hard-switching losses, accurately determining soft-switching losses for wide bandgap semiconductors requires calorimetric measurements. Therefore an automated double pulse testbench is modularly adjusted to enable fast calorimetric measurements within the same setup. For this, a new rapid calorimetric approach is realized utilizing an external optical temperature sensor, which enables accurate measurement during operation without electromagnetic interference and improves the accuracy of loss interpolation. Furthermore, the heatsinkless approach reduces the cooldown times significantly accelerating the overall measurement speed. With the modular setup hard- and soft-switching losses in dependence of the gate-source voltage are characterized for 1200V Silicon Carbide devices.

Abstract

In modern power electronics, wide bandgap semiconductors have an ever-increasing importance for highly efficient, power-dense systems. The extraction of the switching losses is of pristine importance for the modulation of the losses of the final converter and its thermal layout. While there exist a variety of automated test benches for Silicon these are not suitable for the high slew rates present in wide bandgap. In this paper, a fully parametrized and automated double pulse test setup compatible with all discrete packages of Gallium Nitride and Silicon Carbide devices is presented. The setup enables fully automated and fast parameter sweeps in dependence on drain-source current, drain-source, and variable gate-source voltage as well as temperature while maintaining an application-oriented layout of the commutation cell.

Abstract

In this research, we demonstrate a 60 W, 60 V, 3 MHz auto-resonant integrated power oscillator implemented on IMEC’s 650 V GaN-on-SOI MPW process. The monolithic integrated circuit, with dimensions of 2.$5\times$ 2.5mm$^2$, incorporates the switching cell of the so-called Royer-Circuit which can be used both in transmitter (inverter) and receiver (rectifier) circuits for WPT systems. Designed for power levels of 100W, the chip can handle maximum input voltages up to 150V and switching frequencies in a single-digit MHz range. The integrated design as well as MHz switching frequencies allow for a very compact and simple WPT system. This paper describes the operation and functionality of the Royer converter including the processed GaN-Royer IC and addresses important aspects of the integration of the circuit. The operation and performance of the designed IC is demonstrated in operation at resonant frequencies of up to 3MHz and output powers up to 100W at an input voltage of maximum 60V. The whole WPT system, including a Royer converter as transmitter and receiver reaches efficiencies between DC in and DC out up to $= 90\%$. The limitations and further optimizations for such a converter system are discussed at the end of the paper.

Abstract

Virtual prototyping, multi-objective optimization and design automation are increasingly being used to meet the growing demands of modern power electronic applications in terms of efficiency and power density. These concepts are based on accurate loss models of the power semiconductors used. While for hard-switching the double pulse test is an established electrical characterization method, soft-switching losses can only be determined by calorimetric measurements. Despite significant improvements in using transient approaches, calorimetric characterization of soft-switching loss energy is very time-intensive and requires complex measurement setups. This paper presents a new automated calorimetric method with thermal impedance calibration that enables rapid and non-invasive switching loss measurements. Using ultra-fast transient measurements and accelerated cooling phases in between, soft-switching loss maps can be determined based on hundreds of individual readings. The proposed measuring method is validated against hard-switching electrical double pulse test measurements. The method achieves a maximum error of $1.9 \,\%$ for the total loss measurement from $1-9 \,W$ and an average measurement error of $16.5 \,\%$ for the soft-switching energy from $1-4 \,J$ of wide bandgap power semiconductors. In addition to comparing the results of different semiconductor technologies for use in a charger application, the manufacturers' simulation models are also analyzed with respect to soft-switching energy.

Abstract

Emerging electromobility requires a comprehensive simulation environment of the inverter and motor stage to ensure their performance and efficiency. Digital prototypes are critical to shortening development time and reducing costs by providing realistic test scenarios for such systems. The WLTP (Worldwide Harmonized Light Vehicles Test Procedure) is often not simulated but plays an important role, as this cycle reflects real driving conditions and thus enables an accurate assessment of the performance of electric vehicles. This work examines the role of digital prototypes in the context of e-mobility and focuses on the importance of WLTP cycle simulations for application-oriented testing. Furthermore, the focus is on the development of low-voltage inverters based on GaN-HEMT’s and the performance of detailed simulations using Spice, which allows a reasonable tradeoff between physical details and simulation time. The electro-mechanical behavior of a BLDC motor operated at various switching frequencies up to 150 kHz is simulatively compared to real measurement data. Then, the standardized motor test cycle WLTC is simulated to estimate the power consumption in driving cycles. This simulation environment enables sweeping various parameters like switching frequencies and commutation schemes e.g. trapezoidal or sinusoidal. Higher switching frequencies promise a combined efficiency increase of approx. 8 % of the electro-mechanical sub-system in this application-oriented test cycle. This work serves as a basis for new rapid prototyping for small electric vehicles, which can easily be adapted for e.g. 800 V, high-power automotive inverters.

Abstract

By utilizing a digital twin, based on physically-motivated device models and comprehensive time and frequency domain simulations for parasitic extraction, in this work a gate-loop resistor optimization utilizing paralleled 48V, 7mΩ GaN HEMTs in a buck-converter for a 300 kHz, 48V to 24V, high current DC/DC operation up to 80A is presented. Through automated transient simulation and evaluation of both overshoots and switching losses of all four GaN HEMTs, all gate-resistors Rg,on–HS, Rg,off–HS, Rg,on–LS, Rg,off–LS are optimized individually for maximum efficiency or minimal drain and gate voltage overshoots at the switching transients, to extend the life-time of the transistors and minimize device failures and breakdowns. The simulation includes the main parasitic components (power and gate loop inductances), derived from a full-wave electromagnetic simulation up to 3GHz of the assembled PCB, which are crucial for the converter performance and digital twin fidelity. The overshoot-optimized version is resulting in a 35% reduction of the low-side turn-on overshoot with only 0.4% lower efficiency (96.7% instead of 97.1%) at 60A for the efficiency-optimized version. The approach of this work is a promising basis for further optimization with a useful combination between system-level and device-level simulations, necessary for the evaluation of fully automated syntheses of power electronic sub-systems, as well as the evaluation of design spaces.

Abstract

Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a $7\ mØmega$, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a $5\ mØmega$, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both $7\ mØmega$ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the $5\ mØmega$ GaN transistor. With its combination of improved thermal characteristics and low-inductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density.

Abstract

In this work a highly-integrated, 24 V input, dual-output (5 to 1SV up to 1A and −1.3V up to 100mA), low-noise GaN-based DC/DC supply for the gate and drain bias of a GaN solid state power amplifier for E- and W-band applications in space ór phased-array applications is presented. By using two fast-switching GaN half-bridges as the main element of two highly-integrated DC/DC converters for gate and drain bias supply, $\approx$50% higher efficiency and an adjustable drain voltage (e.g. for orbital tracking) can be achieved compared to state-of-the-art solutions (LDOs only). The required drain supply of the GaN SSPA (5 to 18 V with currents up to 1 A) is generated by a 70 m$Ømega$, 100V monolithic GaN half-bridge based buck-converter switching at 3.1 MHz with high gate-resistors $(62Ømega/10Ømega)$, extended filtering (resulting in an ac voltage noise of below 5 mV RMS for most bias points) and efficiencies above 80% for the whole output current range. The gate supply $(-1.3V,\ 100mA)$ is provided by a multi-stage approach to achieve efficient conversion and low noise: In the first stage the battery voltage is down converted to 5 V in a 3.1 MHz buck-converter $(\eta90\ \%)$ with two 3.3 $Ømega, 65V GaN$ transistors, to optimize the efficiency of the second stage. The second stage (switched capacitor, 2 MHz circuit, $\eta\geq$ 80%) converts the voltage to −2 V. A final LDO stage converts the −5V to −1.3 V with $0.8 V$ RMS-noise, to avoid instabilities of the SSPA due to gate bias oscillations. The converter is not actively cooled and does not exceed a local hotspot temperature of 85 °C at any operation point.

Abstract

In this work an approach for a direct experimental comparison of the application-oriented performance between two high current GaN DC/DC converters based on 7mΩ, 100V GaN HEMTs in a commercial off-the-shelf top-cooled package and 5mΩ, 100V GaN HEMTs embedded in a thermally-optimized single-chip package is given. The two packaging versions are compared by a maximally identical implementation of the power and gate loops in a 48V, 300kHz buck converter with two parallel GaN HEMTs. In the single-chip package the die is directly mounted on a 12×6mm2 copper-heat spreader offering a significantly lower thermal resistance to heatsink (1.69KW−1) in comparison to the commercial off-the-shelf version (2.45KW−1). For a direct benchmark, the COTS-based converter has an identical power-loop to the SCP-version with a novel gate-drive concept. Both versions have an efficiency of 96.8% at 65A output current (output power: 1.5kW), while the commercial off-the-shelf version has a better efficiency for lower currents, due to its better hard-switching Figure-of-Merits and therefore lower switching losses and reaches an output current of up to 80A (output power: 1.75kW). A detailed analytical loss breakdown for the different transistors in dependence of the temperature and output current is given to proof the measured current point, where the efficiencies of both converters are identical, since the higher switching losses of the SCP version are compensated by lower conduction losses at higher currents and temperatures compared to the smaller COTS transistor. Finally, an outlook on further improvements for reaching higher output currents and potential converters for a more fair comparison of different thermally optimized SMD packages are given.

Abstract

This paper presents the design and analysis of a high-density two-stage battery charger for mid-power applications like small electric vehicles and high-performance laptops utilizing gallium nitride (GaN) power devices. In addition to adherence of maximum junction temperatures, a thermal analysis is carried out for in-housing operation, which is particularly critical for fanless wall chargers. Design measures include calorimetric semiconductor selection, half-bridge miniaturization, thermally conductive epoxy resin and reference-based convection modeling for thermally optimized component placement using 3D-stacking. Furthermore, the remaining optimization potential of the charger is estimated by virtual prototyping. A 170 W hardware prototype is developed and tested, achieving a two-stage power section efficiency of 95.4% with a maximum switching frequency of 550 kHz. This results in a power density in open-housing operation of 1.6 kW/dm$^3$. Using epoxy resin, copper and graphite heat spreaders, an in-housing operation power density of 1.1 kW/dm$^3$ is achieved with minor reduction of output power due to surface temperature constraints.

Abstract

This work presents the design and analysis of a low-noise, 24 V input and variable output voltage, 2.1 MHz DC/DC converter based on a 100 V, <tex>$70\ mØmega$</tex> Gallium Nitride (GaN) monolithic half-bridge with maximum 1 A converter output current up to 15 V. The converter can be used as variable and highly efficient DC power supply of GaN solid state power amplifiers (SSPA) in E-band as opposed to the conventional low dropout regulators, improving the overall SSPA power efficiency. The converter (0.036 in³) achieves an overall efficiency of above 80 % over nearly the whole output voltage range and a peak efficiency of <tex>$&gt; 91\%$</tex>, depending on the gate resistor, at a power density of above 300 W/in³. The achieved voltage peak amplitude varies from below 20 mV to above 200 mV, again strongly depending on the value of the gate resistor. The AC voltage ripple is below 2 mV for all converter designs, making it suitable for low-noise supply of the power amplifiers drain terminals and to replace the conventional inefficient low-dropout voltage regulators. A comprehensive analysis of the tradeoff between switching speed, efficiency and high-/low frequency voltage noise is carried out to highlight the potential of GaN based low-noise DC/DC supplies. Finally, measurements are performed with different DC supplies (LDO, switch-mode power supply unit, and the GaN DC/DC converter from this work) with an E-band transmission chain to demonstrate the usability of this approach. It can be seen that the GaN DC/DC converter supplies the SSPA with no difference to the state-of-the-art solutions and does not cause any oscillations/instabilities, but can increase the efficiency of the power amplifier by 40 %.

Abstract

This work presents a novel approach for the optimization of a self-oscillating power converter (Royer converter) based on GaN HEMTs for inductively coupled wireless power transfer applications. By combining gallium nitride high electron mobility transistors (HEMT) as power transistors and depletion-mode (silicon) transistors as control transistors, not only the better intrinsic performance of GaN is used, but also all auxiliary supply voltages can be omitted in comparison to the standard silicon transistor-based Royer converter. This paper describes the functional principle with the aid of a simulation based on an inhouse extended power transistor model and optimized transistor parameters. Then it gives insight into the novel prototype and demonstrates the operation at a resonance frequency and an output power of up to 500 kHz and 90 W at 30 V input voltage with peak efficiencies above 94% for the whole wireless power transfer system. Finally, the limitations and further optimizations for such Royer converter systems will be discussed.

Abstract

The design of a compact AC/DC converter for a wide output voltage range imposes stringent challenges regarding electrical and thermal performance. To match these requirements this paper presents the design approach and measurements of a Totem-Pole Power Factor Correction (PFC) and a resonant LLC converter stage, optimized for a maximum average efficiency over a wide operating range. The work deals with the design process itself, which is subdivided into the derivation of the necessary efficiency due to the thermal and geometrical boundary conditions. Further it details the influence of the high packing density and the thermal management on the electrical behavior. A thermally conductive epoxy resin which is designed to meet increasing demands for efficient thermal dissipation has significant unintentional influence on the electrical behavior of the LLC resonant circuit. The root causes are analyzed and verified by measurements.

Abstract

The measurement of switching losses with conventional double pulse tests, especially for modern wide bandgap power semiconductors, is invasive with respect to commutation cell inductance and limited in accuracy by the bandwidth of current and voltage probes. Therefore, calorimetric measurement methods are used to meet the high requirements for the characterization of extremely small soft-switching losses. In this work the noninvasive and fast transient calorimetric measurement method is evaluated for the extended characterization of hard-switching losses. For the first time the transition of the switching losses from short circuit to hard-switching, partial soft-switching, optimal soft-switching and reverse conduction are presented with high measurement accuracy due to variable measurement durations and thermal impedance calibration. In addition, the parasitic influence of switch node capacitance changes on the measurement accuracy is analyzed. The comparison with electrical measurements validates the measurement method and shows the relevance of calorimetric approaches as an alternative to electrical double pulse test measurements for improved loss pre-diction in modern resonant and fast-switching power converters.

Abstract

This paper presents the design and analysis of a high-density two-stage battery charger for mid-power applications like small electric vehicles and high-performance laptops utilizing gallium nitride (GaN) power devices. In addition to adherence of maximum junction temperatures, a thermal analysis is carried out for in-housing operation, which is particularly critical for fanless wall chargers. Design measures include calorimetric semiconductor selection, half-bridge miniaturization, thermally conductive epoxy resin and reference-based convection modeling for thermally optimized component placement using 3D-stacking. Furthermore, the remaining optimization potential of the charger is estimated by virtual prototyping. A 170 W hardware prototype is developed and tested, achieving a two-stage power section efficiency of 95.4 % with a maximum switching frequency of 550 kHz. This results in a power density in open-housing operation of 1.6 kW / dm. Using epoxy resin, copper and graphite heat spreaders, an in-housing operation power density of 1.1 kW / dm is achieved with minor reduction of output power due to surface temperature constraints.

Abstract

In this work a novel approach for an automated calorimetric measurement of soft-switching losses of wide-bandgap semiconductors with the aid of a Peltier element is shown. The Peltier element is used to either cool down or heat up the heat-sink and the device under test in a thermally isolating chamber. The derivation of the losses in dependence of the individual thermal properties as well as a simplified solution is given. Finally, measurements are shown which prove the functional principle for soft-switching losses of SiC and GaN transistors and confirm excellent match between the modeled and calorimetrically determined and electrically measured losses.

Abstract

Hotspots on passively cooled housings of power electronic systems result in early exceeding of surface contact temperatures and therefore in not fully utilizing the maximum loss budget for maximum power density. This paper presents an automated design concept for heat flow control to avoid hotspots at the surface via iterative optimization of the housing wall thickness based on thermal 3D-FEM simulations and geometry variation with Marching Cubes meshing. Basic influencing parameters of the concept are identified and analyzed regarding volume requirements and optimization impact. The experimental results with optimized plastic housings show a significantly more homogeneous surface temperature distribution and a loss budget increase of up to 11 %, which validates the use of the concept for optimization of highly compact systems.

Abstract

This work presents a gate-driver-circuit which operates a LLC-half-bridge based on 650 V gallium-nitride transistors. The gate-driver-circuit reaches a switching frequency up to 20 MHz in no-load operation. Up to a switching frequency of 10 MHz, a HV-voltage of 200 V and an output-power of 70 W the function of the LLC-half-bridge can be proven. At a switching frequency of 1 MHz the converter is able to reach an output power of 500 W. Continuous operation is thermally limited at 10 MHz, because the switching losses (60 W per transistor) cannot be sufficiently dissipated despite zero-voltage-switching. In further development, the thermal path could be improved by heat spreading layer between the transistor-case and a water-cooled heat sink with the usage of ceramic substrates. For the gate-driver-circuit and the LLC-half-bridge only commercially components off the shelf were used.

Abstract

This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is α = 0.00541 /K. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.

Abstract

In this work experimental and simulative proof of a concept for paralleling low voltage and high current Gallium Nitride (GaN) transistors each with a distinct gate booster is presented. For both high-side (HS) and low-side (LS), two 100V 5mΩ normally-off GaN-HEMTs are operated with a driver, which offers separate paths for turn-on and turn-off. In combination with the Kelvin source a minimal gate-loop inductance and stable switching operation is achieved. The HS and LS signals are provided by an isolated half-bridge driver with ultra-low jitter and identical PCB path lengths to ensure equal propagation delay. The half-bridge with paralleled GaN-HEMTs, which is approved by full-wave S-parameter extraction in combination with a comprehensive thermal simulation and a transient simulation based on a physical GaN model, is operated in a 300kHz48V-to-24V buck converter operation up to 54A output current with an overall efficiency of above 95%. The output power of the converter is mainly limited by the thermal performance of the packaging and the PCB and the single gate-contact of the transistors, which is reducing the degrees of freedoms in the layout and introducing significant common source and parasitic inductances.

Abstract

To make the full performance of the intrinsic 100 V, 5mΩ gallium nitride transistors available on system level, in this work an asymmetrical & thermally optimized PCB embedded single chip package with integrated resistance thermometer, high temperature capability and a thermal resistance Rth,j–hs of 3.3KW−1 is characterized in a 48 V to 24 V 300 kHz mild-hybrid DC/DC operation with two paralleled chips in each low- (LS) and high-side (HS). The transistors are mounted on a 4-layer multilayer PCB with 1 mm copper inlays to achieve a high current capability, while allowing narrow logic traces on the same PCB. The designed converter is achieving a light load efficiency of ≥99 % and an efficiency of 97 % at 60 A output current and ≈1.3 kW output power in a 48 V to 24 V 300 kHz buck-converter operation. The on-board temperature readout circuit and the phase output current sensor offer the possibility to extend the GaN transistors to an intelligent power module by the compact and simple sensors.

Abstract

Passively cooled housings for modern power electronic converters with high power density require maximum heat dissipation over little surface area. To determine the power dissipation budget, this paper presents thermal measurement based convection modeling with temperature dependent heat transfer coefficients and the derivation of efficiency requirements for given housing dimensions.

Abstract

This paper presents a characterization of monolithic integrated temperature sensors in a 600 V GaN-on-Si Power IC for half-bridge converters, by performing static and dynamic measurements. The static characterization is realized by steady-state temperature evaluation, while for dynamic characterization several power steps are applied to either one or both high-side and low-side transistors. Compared to a similar half-bridge, which uses external platinum resistors as temperature sensors, the superior performance of the integrated sensors regarding response time (30-fold decrease) is shown. With the integrated temperature sensors in both half-bridge transistors, asymmetric power loss and temperatures were measured. Furthermore, on-line temperature measurements are shown in a resonant-switching half-bridge, where a 0.25 K temperature change was measured after a 50 ns dead-time variation. During continuous hard-switching operation of two GaN power ICs in a half-bridge at 200 V input, 3 A output with up to 99% efficiency and 536W output power, the effect of output voltage variation between 20 V and 180 V on high-side and low-side device temperature increase was measured in real-time.

Abstract

A quasi-threshold voltage measurement setup is implemented in a test bench to allow online parameter observation during power cycling tests for silicon carbide MOSFETs. The threshold voltage is known to change during operation, either temporarily or non-reversibly, due to degradation and trapping phenomena in the MOS-structure. To evaluate different assembly and interconnection technologies, for conditions as close to the real application as possible, an application-oriented power cycling test setup is examined. The proposed test bench allows the measurement of a quasi-threshold voltage under the influence of different off-state drain-source and gate voltages. Measurements show a decrease of quasi-threshold voltage with increasing off-state drain-source voltage and negative gate-source voltage.

Abstract

This paper presents a robust and easy-to-implement approach to measure the junction temperature of SiC power devices using quasi-threshold voltage as temperature sensitive electrical parameter with adjustable temperature sensitivity. The voltage drop across the parasitic inductance between Kelvin and power source is used to trigger the data acquisition circuit. The novelty of the proposed method lies in the concept of variable temperature sensitivity where the robustness decreases with the increase in the sensitivity. This concept proposes a trade-off between temperature sensitivity and robustness. A D flip-flop is used to make the acquisition circuit more robust to prevent false triggering while keeping fast switching speed and low noise susceptibility. Basic simulations, static and dynamic measurements are performed successfully on a commercially available 1.2 kV/120 A power module in a buck converter topology. The effect of DC-link voltage and load current invariance is also verified in this paper.

Abstract

The design of an LLC stage for a wide output voltage range imposes stringent challenges regarding electrical and thermal performance. To match these requirements this paper presents the design approach and measurements of a resonant LLC converter stage, optimized for a maximum average efficiency over a wide operating range.

Abstract

The use of packaging technologies, which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.

Abstract

A detailed accuracy analysis of calorimetric measurements for benchmarking wide bandgap power transistors under soft-switching operation is presented. This paper will present a deeper insight into this method and propose enhancements to ensure higher accuracy of the extracted switching energy by evaluating the whole measurement and calculation chain. Furthermore, the confidence level for the switching energy can be derived for each measurement and the most critical errors of the presented measurement chain can be identified. A benchmarking of the soft-switching energies of different SiC and GaN devices is presented, compared to other work and discussed.