Mathias Weiser

Abstract

Virtual prototyping, multi-objective optimization and design automation are increasingly being used to meet the growing demands of modern power electronic applications in terms of efficiency and power density. These concepts are based on accurate loss models of the power semiconductors used. While for hard-switching the double pulse test is an established electrical characterization method, soft-switching losses can only be determined by calorimetric measurements. Despite significant improvements in using transient approaches, calorimetric characterization of soft-switching loss energy is very time-intensive and requires complex measurement setups. This paper presents a new automated calorimetric method with thermal impedance calibration that enables rapid and non-invasive switching loss measurements. Using ultra-fast transient measurements and accelerated cooling phases in between, soft-switching loss maps can be determined based on hundreds of individual readings. The proposed measuring method is validated against hard-switching electrical double pulse test measurements. The method achieves a maximum error of $1.9 \,\%$ for the total loss measurement from $1-9 \,W$ and an average measurement error of $16.5 \,\%$ for the soft-switching energy from $1-4 \,J$ of wide bandgap power semiconductors. In addition to comparing the results of different semiconductor technologies for use in a charger application, the manufacturers' simulation models are also analyzed with respect to soft-switching energy.

Abstract

In this work an approach for a direct experimental comparison of the application-oriented performance between two high current GaN DC/DC converters based on 7mΩ, 100V GaN HEMTs in a commercial off-the-shelf top-cooled package and 5mΩ, 100V GaN HEMTs embedded in a thermally-optimized single-chip package is given. The two packaging versions are compared by a maximally identical implementation of the power and gate loops in a 48V, 300kHz buck converter with two parallel GaN HEMTs. In the single-chip package the die is directly mounted on a 12×6mm2 copper-heat spreader offering a significantly lower thermal resistance to heatsink (1.69KW−1) in comparison to the commercial off-the-shelf version (2.45KW−1). For a direct benchmark, the COTS-based converter has an identical power-loop to the SCP-version with a novel gate-drive concept. Both versions have an efficiency of 96.8% at 65A output current (output power: 1.5kW), while the commercial off-the-shelf version has a better efficiency for lower currents, due to its better hard-switching Figure-of-Merits and therefore lower switching losses and reaches an output current of up to 80A (output power: 1.75kW). A detailed analytical loss breakdown for the different transistors in dependence of the temperature and output current is given to proof the measured current point, where the efficiencies of both converters are identical, since the higher switching losses of the SCP version are compensated by lower conduction losses at higher currents and temperatures compared to the smaller COTS transistor. Finally, an outlook on further improvements for reaching higher output currents and potential converters for a more fair comparison of different thermally optimized SMD packages are given.

Abstract

This work presents the design and analysis of a low-noise, 24 V input and variable output voltage, 2.1 MHz DC/DC converter based on a 100 V, <tex>$70\ mØmega$</tex> Gallium Nitride (GaN) monolithic half-bridge with maximum 1 A converter output current up to 15 V. The converter can be used as variable and highly efficient DC power supply of GaN solid state power amplifiers (SSPA) in E-band as opposed to the conventional low dropout regulators, improving the overall SSPA power efficiency. The converter (0.036 in³) achieves an overall efficiency of above 80 % over nearly the whole output voltage range and a peak efficiency of <tex>$&gt; 91\%$</tex>, depending on the gate resistor, at a power density of above 300 W/in³. The achieved voltage peak amplitude varies from below 20 mV to above 200 mV, again strongly depending on the value of the gate resistor. The AC voltage ripple is below 2 mV for all converter designs, making it suitable for low-noise supply of the power amplifiers drain terminals and to replace the conventional inefficient low-dropout voltage regulators. A comprehensive analysis of the tradeoff between switching speed, efficiency and high-/low frequency voltage noise is carried out to highlight the potential of GaN based low-noise DC/DC supplies. Finally, measurements are performed with different DC supplies (LDO, switch-mode power supply unit, and the GaN DC/DC converter from this work) with an E-band transmission chain to demonstrate the usability of this approach. It can be seen that the GaN DC/DC converter supplies the SSPA with no difference to the state-of-the-art solutions and does not cause any oscillations/instabilities, but can increase the efficiency of the power amplifier by 40 %.

Abstract

This paper presents the design and analysis of a high-density two-stage battery charger for mid-power applications like small electric vehicles and high-performance laptops utilizing gallium nitride (GaN) power devices. In addition to adherence of maximum junction temperatures, a thermal analysis is carried out for in-housing operation, which is particularly critical for fanless wall chargers. Design measures include calorimetric semiconductor selection, half-bridge miniaturization, thermally conductive epoxy resin and reference-based convection modeling for thermally optimized component placement using 3D-stacking. Furthermore, the remaining optimization potential of the charger is estimated by virtual prototyping. A 170 W hardware prototype is developed and tested, achieving a two-stage power section efficiency of 95.4% with a maximum switching frequency of 550 kHz. This results in a power density in open-housing operation of 1.6 kW/dm$^3$. Using epoxy resin, copper and graphite heat spreaders, an in-housing operation power density of 1.1 kW/dm$^3$ is achieved with minor reduction of output power due to surface temperature constraints.

Abstract

The design of a compact AC/DC converter for a wide output voltage range imposes stringent challenges regarding electrical and thermal performance. To match these requirements this paper presents the design approach and measurements of a Totem-Pole Power Factor Correction (PFC) and a resonant LLC converter stage, optimized for a maximum average efficiency over a wide operating range. The work deals with the design process itself, which is subdivided into the derivation of the necessary efficiency due to the thermal and geometrical boundary conditions. Further it details the influence of the high packing density and the thermal management on the electrical behavior. A thermally conductive epoxy resin which is designed to meet increasing demands for efficient thermal dissipation has significant unintentional influence on the electrical behavior of the LLC resonant circuit. The root causes are analyzed and verified by measurements.

Abstract

This work presents a novel approach for the optimization of a self-oscillating power converter (Royer converter) based on GaN HEMTs for inductively coupled wireless power transfer applications. By combining gallium nitride high electron mobility transistors (HEMT) as power transistors and depletion-mode (silicon) transistors as control transistors, not only the better intrinsic performance of GaN is used, but also all auxiliary supply voltages can be omitted in comparison to the standard silicon transistor-based Royer converter. This paper describes the functional principle with the aid of a simulation based on an inhouse extended power transistor model and optimized transistor parameters. Then it gives insight into the novel prototype and demonstrates the operation at a resonance frequency and an output power of up to 500 kHz and 90 W at 30 V input voltage with peak efficiencies above 94% for the whole wireless power transfer system. Finally, the limitations and further optimizations for such Royer converter systems will be discussed.

Abstract

The measurement of switching losses with conventional double pulse tests, especially for modern wide bandgap power semiconductors, is invasive with respect to commutation cell inductance and limited in accuracy by the bandwidth of current and voltage probes. Therefore, calorimetric measurement methods are used to meet the high requirements for the characterization of extremely small soft-switching losses. In this work the noninvasive and fast transient calorimetric measurement method is evaluated for the extended characterization of hard-switching losses. For the first time the transition of the switching losses from short circuit to hard-switching, partial soft-switching, optimal soft-switching and reverse conduction are presented with high measurement accuracy due to variable measurement durations and thermal impedance calibration. In addition, the parasitic influence of switch node capacitance changes on the measurement accuracy is analyzed. The comparison with electrical measurements validates the measurement method and shows the relevance of calorimetric approaches as an alternative to electrical double pulse test measurements for improved loss pre-diction in modern resonant and fast-switching power converters.

Abstract

In this work a novel approach for an automated calorimetric measurement of soft-switching losses of wide-bandgap semiconductors with the aid of a Peltier element is shown. The Peltier element is used to either cool down or heat up the heat-sink and the device under test in a thermally isolating chamber. The derivation of the losses in dependence of the individual thermal properties as well as a simplified solution is given. Finally, measurements are shown which prove the functional principle for soft-switching losses of SiC and GaN transistors and confirm excellent match between the modeled and calorimetrically determined and electrically measured losses.

Abstract

This paper presents the design and analysis of a high-density two-stage battery charger for mid-power applications like small electric vehicles and high-performance laptops utilizing gallium nitride (GaN) power devices. In addition to adherence of maximum junction temperatures, a thermal analysis is carried out for in-housing operation, which is particularly critical for fanless wall chargers. Design measures include calorimetric semiconductor selection, half-bridge miniaturization, thermally conductive epoxy resin and reference-based convection modeling for thermally optimized component placement using 3D-stacking. Furthermore, the remaining optimization potential of the charger is estimated by virtual prototyping. A 170 W hardware prototype is developed and tested, achieving a two-stage power section efficiency of 95.4 % with a maximum switching frequency of 550 kHz. This results in a power density in open-housing operation of 1.6 kW / dm. Using epoxy resin, copper and graphite heat spreaders, an in-housing operation power density of 1.1 kW / dm is achieved with minor reduction of output power due to surface temperature constraints.

Abstract

Hotspots on passively cooled housings of power electronic systems result in early exceeding of surface contact temperatures and therefore in not fully utilizing the maximum loss budget for maximum power density. This paper presents an automated design concept for heat flow control to avoid hotspots at the surface via iterative optimization of the housing wall thickness based on thermal 3D-FEM simulations and geometry variation with Marching Cubes meshing. Basic influencing parameters of the concept are identified and analyzed regarding volume requirements and optimization impact. The experimental results with optimized plastic housings show a significantly more homogeneous surface temperature distribution and a loss budget increase of up to 11 %, which validates the use of the concept for optimization of highly compact systems.

Abstract

To make the full performance of the intrinsic 100 V, 5mΩ gallium nitride transistors available on system level, in this work an asymmetrical & thermally optimized PCB embedded single chip package with integrated resistance thermometer, high temperature capability and a thermal resistance Rth,j–hs of 3.3KW−1 is characterized in a 48 V to 24 V 300 kHz mild-hybrid DC/DC operation with two paralleled chips in each low- (LS) and high-side (HS). The transistors are mounted on a 4-layer multilayer PCB with 1 mm copper inlays to achieve a high current capability, while allowing narrow logic traces on the same PCB. The designed converter is achieving a light load efficiency of ≥99 % and an efficiency of 97 % at 60 A output current and ≈1.3 kW output power in a 48 V to 24 V 300 kHz buck-converter operation. The on-board temperature readout circuit and the phase output current sensor offer the possibility to extend the GaN transistors to an intelligent power module by the compact and simple sensors.

Abstract

This work presents a gate-driver-circuit which operates a LLC-half-bridge based on 650 V gallium-nitride transistors. The gate-driver-circuit reaches a switching frequency up to 20 MHz in no-load operation. Up to a switching frequency of 10 MHz, a HV-voltage of 200 V and an output-power of 70 W the function of the LLC-half-bridge can be proven. At a switching frequency of 1 MHz the converter is able to reach an output power of 500 W. Continuous operation is thermally limited at 10 MHz, because the switching losses (60 W per transistor) cannot be sufficiently dissipated despite zero-voltage-switching. In further development, the thermal path could be improved by heat spreading layer between the transistor-case and a water-cooled heat sink with the usage of ceramic substrates. For the gate-driver-circuit and the LLC-half-bridge only commercially components off the shelf were used.

Abstract

This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is α = 0.00541 /K. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.

Abstract

In this work experimental and simulative proof of a concept for paralleling low voltage and high current Gallium Nitride (GaN) transistors each with a distinct gate booster is presented. For both high-side (HS) and low-side (LS), two 100V 5mΩ normally-off GaN-HEMTs are operated with a driver, which offers separate paths for turn-on and turn-off. In combination with the Kelvin source a minimal gate-loop inductance and stable switching operation is achieved. The HS and LS signals are provided by an isolated half-bridge driver with ultra-low jitter and identical PCB path lengths to ensure equal propagation delay. The half-bridge with paralleled GaN-HEMTs, which is approved by full-wave S-parameter extraction in combination with a comprehensive thermal simulation and a transient simulation based on a physical GaN model, is operated in a 300kHz48V-to-24V buck converter operation up to 54A output current with an overall efficiency of above 95%. The output power of the converter is mainly limited by the thermal performance of the packaging and the PCB and the single gate-contact of the transistors, which is reducing the degrees of freedoms in the layout and introducing significant common source and parasitic inductances.

Abstract

Passively cooled housings for modern power electronic converters with high power density require maximum heat dissipation over little surface area. To determine the power dissipation budget, this paper presents thermal measurement based convection modeling with temperature dependent heat transfer coefficients and the derivation of efficiency requirements for given housing dimensions.

Abstract

This paper presents a robust and easy-to-implement approach to measure the junction temperature of SiC power devices using quasi-threshold voltage as temperature sensitive electrical parameter with adjustable temperature sensitivity. The voltage drop across the parasitic inductance between Kelvin and power source is used to trigger the data acquisition circuit. The novelty of the proposed method lies in the concept of variable temperature sensitivity where the robustness decreases with the increase in the sensitivity. This concept proposes a trade-off between temperature sensitivity and robustness. A D flip-flop is used to make the acquisition circuit more robust to prevent false triggering while keeping fast switching speed and low noise susceptibility. Basic simulations, static and dynamic measurements are performed successfully on a commercially available 1.2 kV/120 A power module in a buck converter topology. The effect of DC-link voltage and load current invariance is also verified in this paper.

Abstract

This paper presents a characterization of monolithic integrated temperature sensors in a 600 V GaN-on-Si Power IC for half-bridge converters, by performing static and dynamic measurements. The static characterization is realized by steady-state temperature evaluation, while for dynamic characterization several power steps are applied to either one or both high-side and low-side transistors. Compared to a similar half-bridge, which uses external platinum resistors as temperature sensors, the superior performance of the integrated sensors regarding response time (30-fold decrease) is shown. With the integrated temperature sensors in both half-bridge transistors, asymmetric power loss and temperatures were measured. Furthermore, on-line temperature measurements are shown in a resonant-switching half-bridge, where a 0.25 K temperature change was measured after a 50 ns dead-time variation. During continuous hard-switching operation of two GaN power ICs in a half-bridge at 200 V input, 3 A output with up to 99% efficiency and 536W output power, the effect of output voltage variation between 20 V and 180 V on high-side and low-side device temperature increase was measured in real-time.

Abstract

A quasi-threshold voltage measurement setup is implemented in a test bench to allow online parameter observation during power cycling tests for silicon carbide MOSFETs. The threshold voltage is known to change during operation, either temporarily or non-reversibly, due to degradation and trapping phenomena in the MOS-structure. To evaluate different assembly and interconnection technologies, for conditions as close to the real application as possible, an application-oriented power cycling test setup is examined. The proposed test bench allows the measurement of a quasi-threshold voltage under the influence of different off-state drain-source and gate voltages. Measurements show a decrease of quasi-threshold voltage with increasing off-state drain-source voltage and negative gate-source voltage.

Abstract

The design of an LLC stage for a wide output voltage range imposes stringent challenges regarding electrical and thermal performance. To match these requirements this paper presents the design approach and measurements of a resonant LLC converter stage, optimized for a maximum average efficiency over a wide operating range.

Abstract

The use of packaging technologies, which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.

Abstract

A detailed accuracy analysis of calorimetric measurements for benchmarking wide bandgap power transistors under soft-switching operation is presented. This paper will present a deeper insight into this method and propose enhancements to ensure higher accuracy of the extracted switching energy by evaluating the whole measurement and calculation chain. Furthermore, the confidence level for the switching energy can be derived for each measurement and the most critical errors of the presented measurement chain can be identified. A benchmarking of the soft-switching energies of different SiC and GaN devices is presented, compared to other work and discussed.