Jeremy Nuzzo

2023

1. D. Koch u. a., „Highly-Integrated, Low-Noise, Dual-Output GaN DC/DC for GaN Solid State Power Amplifier Supplies in Space Applications“, in 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), in 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA). Dez. 2023, S. 1–6. doi: 10.1109/WiPDA58524.2023.10382198.
   • Zusammenfassung
   • BibTeX

   Zusammenfassung

   In this work a highly-integrated, 24 V input, dual-output (5 to 1SV up to 1A and −1.3V up to 100mA), low-noise GaN-based DC/DC supply for the gate and drain bias of a GaN solid state power amplifier for E- and W-band applications in space ór phased-array applications is presented. By using two fast-switching GaN half-bridges as the main element of two highly-integrated DC/DC converters for gate and drain bias supply, $\approx$50% higher efficiency and an adjustable drain voltage (e.g. for orbital tracking) can be achieved compared to state-of-the-art solutions (LDOs only). The required drain supply of the GaN SSPA (5 to 18 V with currents up to 1 A) is generated by a 70 m$Ømega$, 100V monolithic GaN half-bridge based buck-converter switching at 3.1 MHz with high gate-resistors $(62Ømega/10Ømega)$, extended filtering (resulting in an ac voltage noise of below 5 mV RMS for most bias points) and efficiencies above 80% for the whole output current range. The gate supply $(-1.3V,\ 100mA)$ is provided by a multi-stage approach to achieve efficient conversion and low noise: In the first stage the battery voltage is down converted to 5 V in a 3.1 MHz buck-converter $(\eta90\ \%)$ with two 3.3 $Ømega, 65V GaN$ transistors, to optimize the efficiency of the second stage. The second stage (switched capacitor, 2 MHz circuit, $\eta\geq$ 80%) converts the voltage to −2 V. A final LDO stage converts the −5V to −1.3 V with $0.8 V$ RMS-noise, to avoid instabilities of the SSPA due to gate bias oscillations. The converter is not actively cooled and does not exceed a local hotspot temperature of 85 °C at any operation point.

   BibTeX

   @inproceedings{10382198, abstract = {In this work a highly-integrated, 24 V input, dual-output (5 to 1SV up to 1A and −1.3V up to 100mA), low-noise GaN-based DC/DC supply for the gate and drain bias of a GaN solid state power amplifier for E- and W-band applications in space ór phased-array applications is presented. By using two fast-switching GaN half-bridges as the main element of two highly-integrated DC/DC converters for gate and drain bias supply, $\approx$50% higher efficiency and an adjustable drain voltage (e.g. for orbital tracking) can be achieved compared to state-of-the-art solutions (LDOs only). The required drain supply of the GaN SSPA (5 to 18 V with currents up to 1 A) is generated by a 70 m$\Omega$, 100V monolithic GaN half-bridge based buck-converter switching at 3.1 MHz with high gate-resistors $(62\Omega/10\Omega)$, extended filtering (resulting in an ac voltage noise of below 5 mV RMS for most bias points) and efficiencies above 80% for the whole output current range. The gate supply $(-1.3\mathrm{V},\ \leq 100\mathrm{m}\mathrm{A})$ is provided by a multi-stage approach to achieve efficient conversion and low noise: In the first stage the battery voltage is down converted to 5 V in a 3.1 MHz buck-converter $(\eta\geq 90\ \%)$ with two 3.3 $\Omega, 65\mathrm{V GaN}$ transistors, to optimize the efficiency of the second stage. The second stage (switched capacitor, 2 MHz circuit, $\eta\geq$ 80%) converts the voltage to −2 V. A final LDO stage converts the −5V to −1.3 V with $0.8 \mu \mathrm{V}$ RMS-noise, to avoid instabilities of the SSPA due to gate bias oscillations. The converter is not actively cooled and does not exceed a local hotspot temperature of 85 °C at any operation point.}, author = {Koch, Dominik and Nuzzo, Jeremy and Bosch, Michael and Rueß, Manuel and Wrana, Dominik and Schoch, Benjamin and Kallfass, Ingmar}, booktitle = {2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA)}, doi = {10.1109/WiPDA58524.2023.10382198}, issn = {2687-8577}, month = {12}, pages = {1-6}, title = {Highly-Integrated, Low-Noise, Dual-Output GaN DC/DC for GaN Solid State Power Amplifier Supplies in Space Applications}, year = 2023 }
2. D. Koch, J. Nuzzo, M. C. J. Weiser, und I. Kallfass, „Digital Twin for Gate-Resistor Optimization of Parallel, 100 V, 7 mΩ, GaN HEMTs based on Comprehensive Multi-Domain Simulations and Physically-Motivated Transistor Models“, in 2023 IEEE Design Methodologies Conference (DMC), in 2023 IEEE Design Methodologies Conference (DMC). Sep. 2023, S. 1–5. doi: 10.1109/DMC58182.2023.10412580.
   • Zusammenfassung
   • BibTeX

   Zusammenfassung

   By utilizing a digital twin, based on physically-motivated device models and comprehensive time and frequency domain simulations for parasitic extraction, in this work a gate-loop resistor optimization utilizing paralleled 48V, 7mΩ GaN HEMTs in a buck-converter for a 300 kHz, 48V to 24V, high current DC/DC operation up to 80A is presented. Through automated transient simulation and evaluation of both overshoots and switching losses of all four GaN HEMTs, all gate-resistors Rg,on–HS, Rg,off–HS, Rg,on–LS, Rg,off–LS are optimized individually for maximum efficiency or minimal drain and gate voltage overshoots at the switching transients, to extend the life-time of the transistors and minimize device failures and breakdowns. The simulation includes the main parasitic components (power and gate loop inductances), derived from a full-wave electromagnetic simulation up to 3GHz of the assembled PCB, which are crucial for the converter performance and digital twin fidelity. The overshoot-optimized version is resulting in a 35% reduction of the low-side turn-on overshoot with only 0.4% lower efficiency (96.7% instead of 97.1%) at 60A for the efficiency-optimized version. The approach of this work is a promising basis for further optimization with a useful combination between system-level and device-level simulations, necessary for the evaluation of fully automated syntheses of power electronic sub-systems, as well as the evaluation of design spaces.

   BibTeX

   @inproceedings{10412580, abstract = {By utilizing a digital twin, based on physically-motivated device models and comprehensive time and frequency domain simulations for parasitic extraction, in this work a gate-loop resistor optimization utilizing paralleled 48V, 7mΩ GaN HEMTs in a buck-converter for a 300 kHz, 48V to 24V, high current DC/DC operation up to 80A is presented. Through automated transient simulation and evaluation of both overshoots and switching losses of all four GaN HEMTs, all gate-resistors Rg,on–HS, Rg,off–HS, Rg,on–LS, Rg,off–LS are optimized individually for maximum efficiency or minimal drain and gate voltage overshoots at the switching transients, to extend the life-time of the transistors and minimize device failures and breakdowns. The simulation includes the main parasitic components (power and gate loop inductances), derived from a full-wave electromagnetic simulation up to 3GHz of the assembled PCB, which are crucial for the converter performance and digital twin fidelity. The overshoot-optimized version is resulting in a 35% reduction of the low-side turn-on overshoot with only 0.4% lower efficiency (96.7% instead of 97.1%) at 60A for the efficiency-optimized version. The approach of this work is a promising basis for further optimization with a useful combination between system-level and device-level simulations, necessary for the evaluation of fully automated syntheses of power electronic sub-systems, as well as the evaluation of design spaces.}, author = {Koch, Dominik and Nuzzo, Jeremy and Weiser, Mathias C.J. and Kallfass, Ingmar}, booktitle = {2023 IEEE Design Methodologies Conference (DMC)}, doi = {10.1109/DMC58182.2023.10412580}, month = {09}, pages = {1-5}, title = {Digital Twin for Gate-Resistor Optimization of Parallel, 100 V, 7 mΩ, GaN HEMTs based on Comprehensive Multi-Domain Simulations and Physically-Motivated Transistor Models}, year = 2023 }
3. J. Nuzzo, D. Koch, M. C. J. Weiser, M. Bosch, R. Schnitzler, und I. Kallfass, „Optimized Design of Fast-Switching GaN-based Inverters Utilizing a Digital Prototype in a Standardized Realistic Test Cycle“, in 2023 IEEE Design Methodologies Conference (DMC), in 2023 IEEE Design Methodologies Conference (DMC). Sep. 2023, S. 1–5. doi: 10.1109/DMC58182.2023.10412404.
   • Zusammenfassung
   • BibTeX

   Zusammenfassung

   Emerging electromobility requires a comprehensive simulation environment of the inverter and motor stage to ensure their performance and efficiency. Digital prototypes are critical to shortening development time and reducing costs by providing realistic test scenarios for such systems. The WLTP (Worldwide Harmonized Light Vehicles Test Procedure) is often not simulated but plays an important role, as this cycle reflects real driving conditions and thus enables an accurate assessment of the performance of electric vehicles. This work examines the role of digital prototypes in the context of e-mobility and focuses on the importance of WLTP cycle simulations for application-oriented testing. Furthermore, the focus is on the development of low-voltage inverters based on GaN-HEMT’s and the performance of detailed simulations using Spice, which allows a reasonable tradeoff between physical details and simulation time. The electro-mechanical behavior of a BLDC motor operated at various switching frequencies up to 150 kHz is simulatively compared to real measurement data. Then, the standardized motor test cycle WLTC is simulated to estimate the power consumption in driving cycles. This simulation environment enables sweeping various parameters like switching frequencies and commutation schemes e.g. trapezoidal or sinusoidal. Higher switching frequencies promise a combined efficiency increase of approx. 8 % of the electro-mechanical sub-system in this application-oriented test cycle. This work serves as a basis for new rapid prototyping for small electric vehicles, which can easily be adapted for e.g. 800 V, high-power automotive inverters.

   BibTeX

   @inproceedings{10412404, abstract = {Emerging electromobility requires a comprehensive simulation environment of the inverter and motor stage to ensure their performance and efficiency. Digital prototypes are critical to shortening development time and reducing costs by providing realistic test scenarios for such systems. The WLTP (Worldwide Harmonized Light Vehicles Test Procedure) is often not simulated but plays an important role, as this cycle reflects real driving conditions and thus enables an accurate assessment of the performance of electric vehicles. This work examines the role of digital prototypes in the context of e-mobility and focuses on the importance of WLTP cycle simulations for application-oriented testing. Furthermore, the focus is on the development of low-voltage inverters based on GaN-HEMT’s and the performance of detailed simulations using Spice, which allows a reasonable tradeoff between physical details and simulation time. The electro-mechanical behavior of a BLDC motor operated at various switching frequencies up to 150 kHz is simulatively compared to real measurement data. Then, the standardized motor test cycle WLTC is simulated to estimate the power consumption in driving cycles. This simulation environment enables sweeping various parameters like switching frequencies and commutation schemes e.g. trapezoidal or sinusoidal. Higher switching frequencies promise a combined efficiency increase of approx. 8 % of the electro-mechanical sub-system in this application-oriented test cycle. This work serves as a basis for new rapid prototyping for small electric vehicles, which can easily be adapted for e.g. 800 V, high-power automotive inverters.}, author = {Nuzzo, Jeremy and Koch, Dominik and Weiser, Mathias C.J. and Bosch, Michael and Schnitzler, Ruben and Kallfass, Ingmar}, booktitle = {2023 IEEE Design Methodologies Conference (DMC)}, doi = {10.1109/DMC58182.2023.10412404}, month = {09}, pages = {1-5}, title = {Optimized Design of Fast-Switching GaN-based Inverters Utilizing a Digital Prototype in a Standardized Realistic Test Cycle}, year = 2023 }
4. J. Weimer, N. Weimer, J. Nuzzo, und I. Kallfass, „High power density battery chargers with fast-charging utilizing heat storage“, Applied Thermal Engineering, Bd. 232, S. 121043, Sep. 2023, doi: 10.1016/j.applthermaleng.2023.121043.
   • BibTeX
   • Link

   BibTeX

   @article{Weimer_2023, author = {Weimer, Julian and Weimer, Nicolas and Nuzzo, Jeremy and Kallfass, Ingmar}, doi = {10.1016/j.applthermaleng.2023.121043}, issn = {1359-4311}, journal = {Applied Thermal Engineering}, month = {09}, pages = 121043, publisher = {Elsevier BV}, title = {High power density battery chargers with fast-charging utilizing heat storage}, url = {http://dx.doi.org/10.1016/j.applthermaleng.2023.121043}, volume = 232, year = 2023 }

   Link

   http://dx.doi.org/10.1016/j.applthermaleng.2023.121043