Jeremy Nuzzo

Zusammenfassung

With its low parasitic capacitances, gallium nitride HEMTs in theory enable faster switching transitions than their silicon and silicon carbide MOSFET counterparts. To turn the transistor on and off fast its input capacitance therefore has to be charged and discharged fast too. In doing so, the critical factor is the minimization of the gate loop inductance, which slows down the current in and out of the gate capacitance. In this work, the concept of a coaxial gate loop is presented. Through the cancellation of the magnetic fields during the switching events, the resulting inductance can be reduced and the gate is charged and discharged faster. With this approach, the switching energies of a high voltage GaN Transistor have been decreased by up to 21% through reducing the length of the Miller plateau to 38 ns and therefore increasing the dv/dt during the turn-on transition. Furthermore, this design concept enables a physical separation of the gate driver module and the power module while maintaining the advantages of GaN-based power electronics.

Zusammenfassung

GaN power transistors require packaging concepts that combine low parasitic inductance with excellent thermal management for demanding converter applications. Therefore in this work, a hybrid half-bridge package embedding two discrete 650 V GaN transistors on AIN DBC is proposed, combining module-level thermal performance with the electrical advantages and flexibility of discrete SMD packages and embedding technologies. Static measurements show no significant differences in transfer characteristics, leakage currents (all $I_DS, leak <1 A$ at 600 V), or capacitances compared to reference samples. The package achieves a thermal resistance $R_t h, j - c$ below $0.2 K / W$ and a parasitic power loop inductance below $6 0 0 ~ p H$, with power loop resistance close to twice the nominal $R_DS, on $. This approach enables compact, lowinductive, and thermally efficient half-bridge integration for high-performance power converter applications.

Zusammenfassung

Determining the junction temperature Tj of SiCMOSFETs is of great importance to ensure safe operation in automobiles. State-of-the-art MOSFET thermometry includes methods like lookup tables with insufficient accuracy and computational efficiency. However, thermal neural networks offer a promising solution to the limitations of traditional methods by enabling accurate temperature modeling. This paper presents a thermal neural network approach for automotive threephase inverters, utilizing purely control variables such as the phase currents and DC-link voltage instead of the conventional methods of direct temperature sensing or indirect temperaturesensitive electrical parameter acquisition. It achieves precise temperature estimations with a mean absolute error of 2.09 K, which is in line with the accuracy of the conventional methods and outperforms a lookup table that yields an average absolute error of 5.67 K.

Zusammenfassung

Electromobility poses new challenges for the power grid, particularly due to the varying demand and charging power of numerous electric vehicles at different times. This leads to fluctuating grid loads and makes targeted stabilization measures necessary. The integration of bidirectional on-board chargers enables the use of energy storage in parked vehicles to support grid stability. This is accompanied, however, by additional degradation of the on-board charger caused by rapid power flow variations and the resulting temperature changes occurring in the sub-second range. A bidirectional load profile with microsecond-level resolution over a 24 h temperature simulation for on-board chargers cannot be feasibly generated using conventional simulation methods. It is therefore not possible to estimate the additional degradation in dependence of the provided grid support. This paper presents a parameterized Simulink-based grid simulation framework, combined with a variety of EV usage profiles and charging scenarios. These profiles serve as inputs to a PLECS-based Dual Active Bridge converter, which generates the training dataset for a transformerbased temperature estimation model. By partitioning the 24-hour operating period into 0.2-second intervals, the transformer predicts the junction temperature between each step for every high-voltage SiC transistor with higher temporal resolution. This enables rapid and accurate evaluation of thermal stress and degradation. Using this approach, a remaining useful lifetime of 4.67 years can be estimated for the primary-side SiC transistor under grid support conditions.

Zusammenfassung

This paper presents a 2kW, 100V GaN-based halfbridge power module optimized for high efficiency and power density. The proposed module features a PCB-ceramic stackup combining the advantages of printed circuit board and ceramic substrate technologies. A multilayer flex-PCB design is employed to minimize parasitic inductances, while a highly thermally conductive AIN ceramic interface ensures efficient heat dissipation. These design measures enable high-speed switching operation with output currents up to 70A. Two 100V, $7 m Ømega$ GaN bare dies are connected in parallel and used as highand low-side switches. The flex-PCB power-loop design with a 25 μm thin isolation layer enables the realization of a power-loop inductance of 98.6 pH, supporting voltage transitions reaching 48V/ns with maximal voltage overshoots of 17% of the input voltage. The 250μm thick AlN ceramic baseplate provides a low thermal resistance path to the heat sink, resulting in a simulated thermal resistance of 0.49K/W between the GaN die to the heat sink. Evaluated in a 48 V and 75 V buck converter topology, the power module reaches dc-to-dc efficiencies above 98% and output powers of 1.6 kW at 48 V and 2.2 kW at 75 V with maximum operating temperatures of 65° C. With a power density exceeding 800W/cm3 and the capability to operate at MHz frequencies, this GaN half-bridge module based on the proposed PCB-ceramic stack-up offers significant advantages in terms of efficiency, power density, and thermal performance for high-current switched-mode power supplies.

Zusammenfassung

Back-to-back inverters usually used in dynamic ac power cycling typically consist of one load half-bridge and a DUT half-bridge. The load half-bridge is typically made out of IGBTs, limiting the switching frequency compared to SiC MOSFETs. This work proposes to replace the IGBTs by SiC MOSFETs and to synchronize the switching events. The result is, that an inductor below 5 % of the size necessary for the traditional modulation scheme, to suffice for the same current ripple and switching frequency. This is due to the utilization of the opposition method and use of the freewheeling states. Additionally, switching frequencies can be raised, which corrects the ratio between conduction and switching losses, bringing them closer to typical operation conditions of SiC MOSFETs. Moreover, the thermal load can be shifted independently of the duty-cycle.

Zusammenfassung

This work presents a single gate-drive GaN power electronics building block for scalable high-current systems for dc/dc or dc/ac-conversion based on 100V,7mΩ Schottky GaN transistors. By utilizing a dedicated gate-booster for each transistor (fits within the GaN footprint) maximum switching speeds, low switching losses and improved low load efficiency are achieved. Double-pulse measurements at 48V show identical behavior of the four parallel GaNs with identical switching losses within the measurement accuracy of ≈10% (turn-on) and ≈20% (turn-off), gate voltage waveforms with a worst-case time offset of ≤600ps (turn-off) and 320ps (turn-on) and similar undershoots. Furthermore, the current sharing between the four paralleled GaN transistors is evaluated in double-pulse tests by characterization and simple modeling of the transfer characteristic of each transistor and accurate gate-source and drain-source voltage measurement, showcasing the applicability of the single gate-drive concept.

Zusammenfassung

In this work a highly-integrated, 24 V input, dual-output (5 to 1SV up to 1A and −1.3V up to 100mA), low-noise GaN-based DC/DC supply for the gate and drain bias of a GaN solid state power amplifier for E- and W-band applications in space ór phased-array applications is presented. By using two fast-switching GaN half-bridges as the main element of two highly-integrated DC/DC converters for gate and drain bias supply, $\approx$50% higher efficiency and an adjustable drain voltage (e.g. for orbital tracking) can be achieved compared to state-of-the-art solutions (LDOs only). The required drain supply of the GaN SSPA (5 to 18 V with currents up to 1 A) is generated by a 70 m$Ømega$, 100V monolithic GaN half-bridge based buck-converter switching at 3.1 MHz with high gate-resistors $(62Ømega/10Ømega)$, extended filtering (resulting in an ac voltage noise of below 5 mV RMS for most bias points) and efficiencies above 80% for the whole output current range. The gate supply $(-1.3V,\ 100mA)$ is provided by a multi-stage approach to achieve efficient conversion and low noise: In the first stage the battery voltage is down converted to 5 V in a 3.1 MHz buck-converter $(\eta90\ \%)$ with two 3.3 $Ømega, 65V GaN$ transistors, to optimize the efficiency of the second stage. The second stage (switched capacitor, 2 MHz circuit, $\eta\geq$ 80%) converts the voltage to −2 V. A final LDO stage converts the −5V to −1.3 V with $0.8 V$ RMS-noise, to avoid instabilities of the SSPA due to gate bias oscillations. The converter is not actively cooled and does not exceed a local hotspot temperature of 85 °C at any operation point.

Zusammenfassung

By utilizing a digital twin, based on physically-motivated device models and comprehensive time and frequency domain simulations for parasitic extraction, in this work a gate-loop resistor optimization utilizing paralleled 48V, 7mΩ GaN HEMTs in a buck-converter for a 300 kHz, 48V to 24V, high current DC/DC operation up to 80A is presented. Through automated transient simulation and evaluation of both overshoots and switching losses of all four GaN HEMTs, all gate-resistors Rg,on–HS, Rg,off–HS, Rg,on–LS, Rg,off–LS are optimized individually for maximum efficiency or minimal drain and gate voltage overshoots at the switching transients, to extend the life-time of the transistors and minimize device failures and breakdowns. The simulation includes the main parasitic components (power and gate loop inductances), derived from a full-wave electromagnetic simulation up to 3GHz of the assembled PCB, which are crucial for the converter performance and digital twin fidelity. The overshoot-optimized version is resulting in a 35% reduction of the low-side turn-on overshoot with only 0.4% lower efficiency (96.7% instead of 97.1%) at 60A for the efficiency-optimized version. The approach of this work is a promising basis for further optimization with a useful combination between system-level and device-level simulations, necessary for the evaluation of fully automated syntheses of power electronic sub-systems, as well as the evaluation of design spaces.

Zusammenfassung

Emerging electromobility requires a comprehensive simulation environment of the inverter and motor stage to ensure their performance and efficiency. Digital prototypes are critical to shortening development time and reducing costs by providing realistic test scenarios for such systems. The WLTP (Worldwide Harmonized Light Vehicles Test Procedure) is often not simulated but plays an important role, as this cycle reflects real driving conditions and thus enables an accurate assessment of the performance of electric vehicles. This work examines the role of digital prototypes in the context of e-mobility and focuses on the importance of WLTP cycle simulations for application-oriented testing. Furthermore, the focus is on the development of low-voltage inverters based on GaN-HEMT’s and the performance of detailed simulations using Spice, which allows a reasonable tradeoff between physical details and simulation time. The electro-mechanical behavior of a BLDC motor operated at various switching frequencies up to 150 kHz is simulatively compared to real measurement data. Then, the standardized motor test cycle WLTC is simulated to estimate the power consumption in driving cycles. This simulation environment enables sweeping various parameters like switching frequencies and commutation schemes e.g. trapezoidal or sinusoidal. Higher switching frequencies promise a combined efficiency increase of approx. 8 % of the electro-mechanical sub-system in this application-oriented test cycle. This work serves as a basis for new rapid prototyping for small electric vehicles, which can easily be adapted for e.g. 800 V, high-power automotive inverters.